vm.fail
cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
1exception Icepick_error of string
2
3type prime_strategy =
4 | Prime_temporal
5 | Prime_prefetcht2
6 | Prime_prefetchnta
7 | Prime_nt_store
8
9type access_pattern =
10 | Pattern_sequential
11 | Pattern_reverse
12 | Pattern_strided
13 | Pattern_pointer_chase
14
15module Topology : sig
16 type t
17
18 val discover : unit -> t
19 val l3_ways : t -> int
20 val l3_size : t -> int
21 val way_size : t -> int
22 val max_clos : t -> int
23 val ccx_count : t -> int
24 val cat_supported : t -> bool
25end
26
27module Region : sig
28 type t
29
30 val lock : Topology.t -> size:int -> clos:int -> ?numa:int -> ?huge_pages:bool -> ?verify:bool ->
31 ?prime_strategy:prime_strategy -> ?access_pattern:access_pattern ->
32 ?stride:int -> ?prime_iterations:int -> unit -> t
33 val unlock : t -> unit
34 val ptr : t -> nativeint
35 val size : t -> int
36 val clos : t -> int
37 val to_bigarray_float64 : t -> (float, Bigarray.float64_elt, Bigarray.c_layout) Bigarray.Array1.t
38end
39
40module Latency_stats : sig
41 type t = {
42 mean_ns : int;
43 stddev_ns : int;
44 p50_ns : int;
45 p99_ns : int;
46 p999_ns : int;
47 min_ns : int;
48 max_ns : int;
49 }
50end
51
52module Monitor : sig
53 type t
54
55 val start : Region.t -> t
56 val start_ex : Region.t -> pmu_poll_ns:int -> probe_ns:int -> miss_thresh:int -> t
57 val stop : t -> unit
58 val eviction_count : t -> int
59 val reprime_count : t -> int
60 val is_degraded : t -> bool
61end
62
63val verify : Region.t -> Latency_stats.t
64val bench : nativeint -> size:int -> iterations:int -> Latency_stats.t