cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
1.1 kB
icepick#
icepick use cache ways from the llc using cat/rdt msr configuration. target memory regions are primed into isolated clos partitions to prevent eviction by competing workloads. i als found it personally useful for pinning cryptographic state against side-channel probing + eliminating tail latency in hot paths
build#
make
dune build
usage#
icepick topology # enumerate l3 geometry, way count, clos availability
icepick lock -s 4M -c 1 -v # allocate 4mb into clos 1, verify residency
icepick bench -s 2M # compare locked vs unlocked access latency
icepick status # dump current clos mask assignments
c api:
icepick_topology_t *topo;
icepick_discover_topology(&topo);
icepick_config_t cfg = { .size = 4*1024*1024, .clos_id = 1, .huge_pages = true };
icepick_region_t *region;
icepick_lock(topo, &cfg, ®ion);
void *ptr = icepick_region_ptr(region);
ocaml:
let topo = Icepick.Topology.discover () in
let region = Icepick.Region.lock topo ~size:0x400000 ~clos:1 () in
let ptr = Icepick.Region.ptr region in