vm.fail
cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
1exception Icepick_error of string
2
3module Topology : sig
4 type t
5
6 val discover : unit -> t
7 val l3_ways : t -> int
8 val l3_size : t -> int
9 val way_size : t -> int
10 val max_clos : t -> int
11 val ccx_count : t -> int
12 val cat_supported : t -> bool
13end
14
15module Region : sig
16 type t
17
18 val lock : Topology.t -> size:int -> clos:int -> ?numa:int -> ?huge_pages:bool -> ?verify:bool -> unit -> t
19 val unlock : t -> unit
20 val ptr : t -> nativeint
21 val size : t -> int
22 val clos : t -> int
23 val to_bigarray_float64 : t -> (float, Bigarray.float64_elt, Bigarray.c_layout) Bigarray.Array1.t
24end
25
26module Latency_stats : sig
27 type t = {
28 mean_ns : int;
29 stddev_ns : int;
30 p50_ns : int;
31 p99_ns : int;
32 p999_ns : int;
33 min_ns : int;
34 max_ns : int;
35 }
36end
37
38val verify : Region.t -> Latency_stats.t
39val bench : nativeint -> size:int -> iterations:int -> Latency_stats.t