vm.fail
cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
1.2 kB
39 lines
1# icepick
2
3kernel module for l3 cache pseudo-locking via cat and wc-mapped i/o space.
4
5## overview
6
7icepick exposes a character device for pinning data into isolated l3 cache ways. maps physical i/o space with write-combining via ioremap_wc and mtrr configuration, then primes cache lines using prefetcht2 and temporal loads. cat schemata configured through resctrl sysfs. pmu-based eviction monitoring via perf_event (amd zen l3 miss counter 0x0104e). useful for side-channel isolation or latency-critical data structures requiring deterministic cache residency.
8
9requires cat-capable silicon (amd zen2+), resctrl mounted, and kernel headers for kbuild.
10
11## build
12
13```
14make
15```
16
17outputs `icepick.ko` kernel module.
18
19## usage
20
21```
22insmod icepick.ko
23chmod 666 /dev/cachemem
24
25echo "sensitive data" > /dev/cachemem # lock into l3 way 0
26cat /dev/cachemem # read back, integrity check
27dmesg | grep ICEPICK # check residency/eviction logs
28
29rmmod icepick
30```
31
32ioctl flush:
33
34```c
35#define ICEPICK_IOC_MAGIC 'k'
36#define ICEPICK_FLUSH_CACHE _IOW(ICEPICK_IOC_MAGIC, 1, char *)
37
38ioctl(fd, ICEPICK_FLUSH_CACHE, "please flush my cachelines");
39```