vm.fail
cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
1exception Icepick_error of string
2
3type prime_strategy =
4 | Prime_temporal
5 | Prime_prefetcht2
6 | Prime_prefetchnta
7 | Prime_nt_store
8
9type access_pattern =
10 | Pattern_sequential
11 | Pattern_reverse
12 | Pattern_strided
13 | Pattern_pointer_chase
14
15type core_type =
16 | Core_any
17 | Core_pcore
18 | Core_ecore
19
20module Topology : sig
21 type t
22
23 val discover : unit -> t
24 val l3_ways : t -> int
25 val l3_size : t -> int
26 val way_size : t -> int
27 val max_clos : t -> int
28 val ccx_count : t -> int
29 val cat_supported : t -> bool
30 val mba_supported : t -> bool
31 val mba_is_linear : t -> bool
32 val max_mba_thrtl : t -> int
33 val is_hybrid : t -> bool
34 val pcore_count : t -> int
35 val ecore_count : t -> int
36end
37
38module Region : sig
39 type t
40
41 val lock : Topology.t -> size:int -> clos:int -> ?numa:int -> ?huge_pages:bool -> ?verify:bool ->
42 ?prime_strategy:prime_strategy -> ?access_pattern:access_pattern ->
43 ?stride:int -> ?prime_iterations:int -> ?mba_throttle:int ->
44 ?core_type:core_type -> unit -> t
45 val unlock : t -> unit
46 val ptr : t -> nativeint
47 val size : t -> int
48 val clos : t -> int
49 val to_bigarray_float64 : t -> (float, Bigarray.float64_elt, Bigarray.c_layout) Bigarray.Array1.t
50end
51
52module Latency_stats : sig
53 type t = {
54 mean_ns : int;
55 stddev_ns : int;
56 p50_ns : int;
57 p99_ns : int;
58 p999_ns : int;
59 min_ns : int;
60 max_ns : int;
61 }
62end
63
64module Monitor : sig
65 type t
66
67 val start : Region.t -> t
68 val start_ex : Region.t -> pmu_poll_ns:int -> probe_ns:int -> miss_thresh:int -> t
69 val stop : t -> unit
70 val eviction_count : t -> int
71 val reprime_count : t -> int
72 val is_degraded : t -> bool
73end
74
75val verify : Region.t -> Latency_stats.t
76val bench : nativeint -> size:int -> iterations:int -> Latency_stats.t