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logic pro compatible fpga based logic analyzer
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picologic
/
gateware
7 files
at
main
Kieran Klukas
Add FPGA-USB-Device core and patched non-tristate variant
6w ago
672d3bf7
__init__.py
Add FPGA-USB-Device core and patched non-tristate variant - Add FPGA-USB-Device as submodule (pure Verilog USB FS device core) - Create usbfs_core_top_patched.v: replaces inout tristate with explicit TRELLIS_IO BIDIR buffers for Yosys/ECP5 compatibility - Update picologic_top.v with debug LEDs and OSCG internal oscillator - Hardware testing confirmed: Icepi Zero USB ports not electrically connected to FPGA pins on this board revision. Official usbmouse example also fails to detect USB devices. Gateware verified working (LEDs, PLL, IO buffers all functional). Need working board to proceed. 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
ep1_handler.py
Add Saleae Logic 8 emulator gateware for Icepi Zero Initial FPGA gateware to emulate a Saleae Logic 8 (VID 21A9:PID 1004) on the Icepi Zero ECP5 board via Full-Speed USB using LUNA. Includes USB device descriptors, EP1 command handler state machine (9 opcodes), test pattern generator, pin constraints, build scripts, Nix flake, and unit tests. Toolchain verified with oss-cad-suite (Yosys 0.64, nextpnr-ecp5, Amaranth 0.4.5, LUNA 0.1.1). 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
picologic_top.v
Add FPGA-USB-Device core and patched non-tristate variant - Add FPGA-USB-Device as submodule (pure Verilog USB FS device core) - Create usbfs_core_top_patched.v: replaces inout tristate with explicit TRELLIS_IO BIDIR buffers for Yosys/ECP5 compatibility - Update picologic_top.v with debug LEDs and OSCG internal oscillator - Hardware testing confirmed: Icepi Zero USB ports not electrically connected to FPGA pins on this board revision. Official usbmouse example also fails to detect USB devices. Gateware verified working (LEDs, PLL, IO buffers all functional). Need working board to proceed. 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
test_pattern.py
Add Saleae Logic 8 emulator gateware for Icepi Zero Initial FPGA gateware to emulate a Saleae Logic 8 (VID 21A9:PID 1004) on the Icepi Zero ECP5 board via Full-Speed USB using LUNA. Includes USB device descriptors, EP1 command handler state machine (9 opcodes), test pattern generator, pin constraints, build scripts, Nix flake, and unit tests. Toolchain verified with oss-cad-suite (Yosys 0.64, nextpnr-ecp5, Amaranth 0.4.5, LUNA 0.1.1). 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
top.py
Add Verilog USB test and official LPF; document hardware finding - Add picologic_top.v: minimal Verilog USB device test with explicit TRELLIS_IO buffers, pull-up control, and LED status indicators - Replace custom LPF with official icepi-zero-v1_3.lpf from upstream - Fix top.py USB clock domains and connect signal - Hardware testing confirmed: FPGA programming and LED IO work correctly, but USB D+/D- does not enumerate on either GPIO USB port despite correct pin mapping (F15/E16/G15). Likely board-level issue with USB-C connector wiring or ESD protection. 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
usb_device.py
Wire up LUNA USB endpoints and generate working bitstream - Use LatticeECP5Platform from amaranth.vendor for proper I/O handling - Add usb/usb_io clock domains (12 MHz derived from 50 MHz sync) - Wire EP1 OUT stream to command handler, EP1 IN to response path - Wire test pattern generator to EP2 IN when capture is active - Fix USB resource naming (d_p/d_n for LUNA GatewarePHY compat) - Fix descriptor BCD format and package name (BG256) - Verified: synthesis (2285 LUTs, 9%), PnR, bitstream (136KB) 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
usbfs_core_top_patched.v
Add FPGA-USB-Device core and patched non-tristate variant - Add FPGA-USB-Device as submodule (pure Verilog USB FS device core) - Create usbfs_core_top_patched.v: replaces inout tristate with explicit TRELLIS_IO BIDIR buffers for Yosys/ECP5 compatibility - Update picologic_top.v with debug LEDs and OSCG internal oscillator - Hardware testing confirmed: Icepi Zero USB ports not electrically connected to FPGA pins on this board revision. Official usbmouse example also fails to detect USB devices. Gateware verified working (LEDs, PLL, IO buffers all functional). Need working board to proceed. 💘 Generated with Crush Assisted-by: Crush:qwen3.7-max
1 month ago
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