cache line locking on AMD x86_64 utilising L3 CAT pseudo-locking
integrate intel mba via ia32_l2_qos_cfg for memory bandwidth isolation alongside cat
author
vm.fail
date
(Jan 18, 2026, 3:21 AM UTC)
commit
d93b499e
d93b499ebd7c274acfca9c016c31f0bb26317712
parent
4163caec
4163caec75d82a77b0c94d849f104967ac2a047e
vm.fail
date
(Jan 18, 2026, 3:21 AM UTC)
commit
d93b499e
d93b499ebd7c274acfca9c016c31f0bb26317712
parent
4163caec
4163caec75d82a77b0c94d849f104967ac2a047e
+79
-2
+9
-1
bindings/ocaml/icepick.ml
+9
-1
bindings/ocaml/icepick.ml
···
40
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let max_clos = foreign "icepick_topology_max_clos" (t @-> returning uint)
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let ccx_count = foreign "icepick_topology_ccx_count" (t @-> returning uint)
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let cat_supported = foreign "icepick_topology_cat_supported" (t @-> returning bool)
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+
let mba_supported = foreign "icepick_topology_mba_supported" (t @-> returning bool)
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+
let mba_is_linear = foreign "icepick_topology_mba_is_linear" (t @-> returning bool)
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+
let max_mba_thrtl = foreign "icepick_topology_max_mba_thrtl" (t @-> returning uint)
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end
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module Region = struct
···
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let access_pattern = field t "access_pattern" int
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let stride_bytes = field t "stride_bytes" size_t
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let prime_iterations = field t "prime_iterations" uint
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+
let mba_throttle = field t "mba_throttle" uint
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let () = seal t
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end
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···
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let max_clos t = Unsigned.UInt.to_int (C.Topology.max_clos t.ptr)
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let ccx_count t = Unsigned.UInt.to_int (C.Topology.ccx_count t.ptr)
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let cat_supported t = C.Topology.cat_supported t.ptr
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+
let mba_supported t = C.Topology.mba_supported t.ptr
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+
let mba_is_linear t = C.Topology.mba_is_linear t.ptr
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+
let max_mba_thrtl t = Unsigned.UInt.to_int (C.Topology.max_mba_thrtl t.ptr)
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end
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module Latency_stats = struct
···
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let lock topo ~size ~clos ?(numa = -1) ?(huge_pages = true) ?(verify = false)
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?(prime_strategy = Prime_temporal) ?(access_pattern = Pattern_sequential)
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-
?(stride = 0) ?(prime_iterations = 3) () =
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+
?(stride = 0) ?(prime_iterations = 3) ?(mba_throttle = 0) () =
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let cfg = make C.Config.t in
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setf cfg C.Config.size (Unsigned.Size_t.of_int size);
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setf cfg C.Config.clos_id (Unsigned.UInt.of_int clos);
···
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setf cfg C.Config.access_pattern (access_pattern_to_int access_pattern);
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setf cfg C.Config.stride_bytes (Unsigned.Size_t.of_int stride);
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setf cfg C.Config.prime_iterations (Unsigned.UInt.of_int prime_iterations);
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+
setf cfg C.Config.mba_throttle (Unsigned.UInt.of_int mba_throttle);
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let ptr_ref = allocate C.Region.t (from_voidp void null) in
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let ret = C.lock topo.Topology.ptr (addr cfg) ptr_ref in
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C.check_error ret;
+4
-1
bindings/ocaml/icepick.mli
+4
-1
bindings/ocaml/icepick.mli
···
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val max_clos : t -> int
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val ccx_count : t -> int
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val cat_supported : t -> bool
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+
val mba_supported : t -> bool
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+
val mba_is_linear : t -> bool
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+
val max_mba_thrtl : t -> int
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end
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module Region : sig
···
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val lock : Topology.t -> size:int -> clos:int -> ?numa:int -> ?huge_pages:bool -> ?verify:bool ->
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?prime_strategy:prime_strategy -> ?access_pattern:access_pattern ->
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-
?stride:int -> ?prime_iterations:int -> unit -> t
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+
?stride:int -> ?prime_iterations:int -> ?mba_throttle:int -> unit -> t
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val unlock : t -> unit
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val ptr : t -> nativeint
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val size : t -> int
+4
include/icepick.h
+4
include/icepick.h
···
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icepick_access_pattern_t access_pattern;
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size_t stride_bytes;
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unsigned prime_iterations;
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+
unsigned mba_throttle;
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} icepick_config_t;
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typedef struct {
···
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unsigned icepick_topology_max_clos(const icepick_topology_t *topo);
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unsigned icepick_topology_ccx_count(const icepick_topology_t *topo);
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bool icepick_topology_cat_supported(const icepick_topology_t *topo);
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+
bool icepick_topology_mba_supported(const icepick_topology_t *topo);
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+
bool icepick_topology_mba_is_linear(const icepick_topology_t *topo);
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+
unsigned icepick_topology_max_mba_thrtl(const icepick_topology_t *topo);
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int icepick_lock(icepick_topology_t *topo, const icepick_config_t *cfg, icepick_region_t **region);
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int icepick_unlock(icepick_region_t *region);
+12
src/clos.c
+12
src/clos.c
···
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{
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return default_mask;
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}
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+
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+
int mba_configure(int msr_fd, unsigned clos_id, unsigned throttle)
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+
{
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+
if (clos_id >= MAX_CLOS)
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+
return ICEPICK_E_INVALID;
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+
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+
if (throttle == 0)
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+
return 0;
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+
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uint32_t msr = MSR_IA32_MBA_THRTL_BASE + clos_id;
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return msr_write(msr_fd, msr, throttle);
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}
+8
src/internal.h
+8
src/internal.h
···
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#define MSR_IA32_PQR_ASSOC 0xC8F
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#define MSR_IA32_L3_QOS_MASK_0 0xC90
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+
#define MSR_IA32_L2_QOS_CFG 0xC82
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#define MSR_IA32_MBA_THRTL_BASE 0xD50
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#define CACHE_LINE_SIZE 64
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#define MAX_CLOS 16
···
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struct icepick_topology {
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bool cat_supported;
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+
bool mba_supported;
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+
bool mba_is_linear;
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unsigned l3_ways;
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size_t l3_size;
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size_t way_size;
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unsigned max_clos;
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+
unsigned max_mba_thrtl;
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unsigned ccx_count;
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uint32_t default_way_mask;
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int ccx_numa_node[MAX_CCXS];
···
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unsigned clos_id;
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int numa_node;
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uint32_t way_mask;
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+
unsigned mba_throttle;
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icepick_topology_t *topo;
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struct icepick_monitor *monitor;
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icepick_prime_strategy_t prime_strategy;
···
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icepick_prime_strategy_t strategy, icepick_access_pattern_t pattern,
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size_t stride);
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int monitor_perf_open(int cpu, bool is_amd);
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+
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int mba_configure(int msr_fd, unsigned clos_id, unsigned throttle);
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#endif
+9
src/lock.c
+9
src/lock.c
···
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r->clos_id = cfg->clos_id;
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r->numa_node = cfg->numa_node;
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r->way_mask = way_mask;
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+
r->mba_throttle = cfg->mba_throttle;
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r->topo = topo;
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r->size = ways_needed * topo->way_size;
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r->monitor = NULL;
···
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ret = clos_configure_mask(msr_fd, cfg->clos_id, way_mask);
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if (ret < 0)
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goto cleanup;
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+
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if (topo->mba_supported && cfg->mba_throttle > 0) {
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ret = mba_configure(msr_fd, cfg->clos_id, cfg->mba_throttle);
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+
if (ret < 0)
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goto cleanup;
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}
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ret = clos_associate_thread(msr_fd, cfg->clos_id);
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if (ret < 0)
···
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if (msr_fd >= 0) {
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clos_release(region->clos_id);
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clos_configure_mask(msr_fd, region->clos_id, 0);
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+
if (region->topo->mba_supported && region->mba_throttle > 0)
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+
mba_configure(msr_fd, region->clos_id, 0);
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clos_configure_mask(msr_fd, 0, clos_get_default_mask());
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msr_close(msr_fd);
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}
+33
src/topology.c
+33
src/topology.c
···
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return true;
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}
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+
static bool detect_mba_support(icepick_topology_t *topo)
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+
{
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uint32_t eax, ebx, ecx, edx;
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+
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cpuid(0x10, 0, &eax, &ebx, &ecx, &edx);
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if (!(ebx & (1 << 3)))
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return false;
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+
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cpuid(0x10, 3, &eax, &ebx, &ecx, &edx);
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+
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+
topo->max_mba_thrtl = (eax & 0xFFF) + 1;
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topo->mba_is_linear = (ecx & (1 << 2)) != 0;
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+
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return true;
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+
}
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+
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static void detect_amd_cache_topology(icepick_topology_t *topo)
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{
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uint32_t eax, ebx, ecx, edx;
···
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149
return ICEPICK_E_NO_CAT;
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}
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+
t->mba_supported = detect_mba_support(t);
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+
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if (is_amd_cpu())
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detect_amd_cache_topology(t);
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else
···
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{
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return topo->cat_supported;
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}
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+
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+
bool icepick_topology_mba_supported(const icepick_topology_t *topo)
206
+
{
207
+
return topo->mba_supported;
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+
}
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+
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+
bool icepick_topology_mba_is_linear(const icepick_topology_t *topo)
211
+
{
212
+
return topo->mba_is_linear;
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+
}
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+
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+
unsigned icepick_topology_max_mba_thrtl(const icepick_topology_t *topo)
216
+
{
217
+
return topo->max_mba_thrtl;
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+
}