ChrisPVille/jtaglet
1
1
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
Easy-to-use JTAG TAP and Debug Controller core written in Verilog
12 commits 1 branch 0 tags 42 KiB
  • Verilog 100%
Find a file
Exact
Christopher Parish 6cccf69db0
 User data and opcode now properly use parameters
2018-11-25 21:05:23 -05:00
examples Make no assumptions about the availability of I or D mem. Should make multi-cycle CPU integration easier. 2018-01-21 21:56:51 -05:00
jtaglet Broke up some of the logic for clarity 2018-01-21 11:47:36 -05:00
jtaglet.v User data and opcode now properly use parameters 2018-11-25 21:05:23 -05:00
LICENSE Initial commit 2018-01-12 18:07:51 -05:00
README.md Update README.md 2018-01-12 20:03:16 -05:00

README.md

JTAGlet

Easy-to-use JTAG TAP and Debug Controller core written in Verilog