Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
- Verilog 68.3%
- SystemVerilog 25.3%
- Tcl 4.2%
- Shell 1.5%
- Stata 0.7%
| mig_example.srcs | ||
| .gitignore | ||
| mig.ucf | ||
| mig_example.xpr | ||
| Nexys 4 Onboard DDR2 MIG Configuration.odt | ||
| Nexys 4 Onboard DDR2 MIG Configuration.pdf | ||
| README.md | ||
Xilinx MIG Example
This project serves as a simple reference design for using the onboard DDR2 memory with Xilinx MIG IP of the Nexys 4 DDR / Nexys A7 FPGA Trainer board.
The included step-by-step PDF guide walks through the configuration process.