ChrisPVille/raisin64-cpu
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98 commits 1 branch 2 tags 158 KiB
  • Verilog 87.5%
  • Assembly 6.9%
  • SystemVerilog 2.9%
  • Python 1.6%
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Christopher Parish 4266e36783 Added simple halt and reset scripts
2019-03-27 20:26:12 -04:00
rtl Fixed reset signal in JTAG core 2019-03-27 20:23:01 -04:00
support Added simple halt and reset scripts 2019-03-27 20:26:12 -04:00
tb Added some notes and DDR2 test program 2019-03-13 20:51:34 -04:00
README.md Create README.md 2018-10-07 13:12:38 -04:00

README.md

raisin64-cpu