ChrisPVille/raisin64-nexys4ddr
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Reference implementation of the Raisin64 on a Nexys 4 DDR board
22 commits 1 branch 2 tags 3.5 MiB
  • VHDL 51.9%
  • Verilog 42.5%
  • SystemVerilog 4.4%
  • Tcl 0.8%
  • Shell 0.2%
  • Other 0.1%
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Christopher Parish 76e0c9045c Fixed clock startup problems, clock crossing problems, reset problems, and memory read corruption during refresh.
2019-03-27 20:24:50 -04:00
cpu@c7babefddf Fixed clock startup problems, clock crossing problems, reset problems, and memory read corruption during refresh. 2019-03-27 20:24:50 -04:00
raisin64-nexys4ddr.srcs Fixed clock startup problems, clock crossing problems, reset problems, and memory read corruption during refresh. 2019-03-27 20:24:50 -04:00
software Added some status info 2019-03-16 22:02:25 -04:00
vga Added VGA and updated CPU to v0.0.2 2018-12-09 02:58:30 -05:00
.gitignore Unignore project file 2018-10-30 18:27:57 -04:00
.gitmodules initial commit 2018-10-27 16:52:13 -04:00
LICENSE Initial commit 2018-10-27 16:20:42 -04:00
raisin64-nexys4ddr.xpr Fixed clock startup problems, clock crossing problems, reset problems, and memory read corruption during refresh. 2019-03-27 20:24:50 -04:00
README.md Initial commit 2018-10-27 16:20:42 -04:00

README.md

raisin64-nexys4ddr

Reference implementation of the Raisin64 on a Nexys 4 DDR board